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data sheet ics8430s10byi-03 revision a february 22 , 2011 1 ?2011 integrated device technology, inc. clock generator for cavium processors ics8430s10i-03 general description the ics8430s10i-03 is a pll-based clock generator specifically designed for cavium networks soc processors. this high performance device is optimized to generate the processor core reference clock, the ddr reference clocks, the pci/pci-x bus clocks, and the clocks for both the gigabit ethernet mac and phy. the clock generator offers low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the cn30xx/cn31xx/cn38xx/cn58xx processors. the output frequencies are generated from a 25mh z external input source or an external 25mhz parallel resonant crystal. the extended temperature range of the ics8430s10i-03 supports telecommunication, networking, and storage requirements. applications ? systems using cavium processors ? cpe gateway design ? home media servers ? 802.11n ap or gateway ? soho secure gateway ? soho sme gateway ? wireless soho and sme vpn solutions ? wired and wireless network security ? web servers and exchange servers features ? one selectable differential output pair for ddr 533/400/667, lvpecl, lvds interface levels ? nine lvcmos/ lvttl outputs, 23 ? typical output impedance ? selectable external crystal or differential input source ? crystal oscillator interface designed for 25mhz, parallel resonant crystal ? differential input pair (pclk, npclk) accepts lvpecl, lvds, cml, sstl input levels ? internal resistor bias on npclk pin allows the user to drive pclk input with external single-ended (lvcmos/ lvttl) input levels ? power supply modes: core / output 3.3v / 3.3v lvds, lvpecl, lvcmos 3.3v / 2.5v lvcmos ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package pin assignment 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 qc 48 47 46 45 44 43 42 41 40 39 38 37 v qd0 qd1 gnd gnd v ddo_b qb0 v dd noe_d gnd npll_ sel xtal _in xtal _out nxtal _ sel pclk npclk noe_c noe_b gnd v dd noe_a noe_ref core_sel spi_sel 1 spi_sel0 ddr_sel 1 ddr_sel0 pci_sel1 pci_sel0 v dda nlvds_sel 48-pin tqfp, e- pad 7mm x 7mm x 1mm package body y package top view nqa qa v d d v ddo_b qb1 ddo_cd 36 35 34 33 32 31 30 29 28 27 26 25 v ddo_ref noe_e gnd gnd v ddo_ref qe v ddo_e gnd qref2 qref1 qref0 ics8430s10i-03 48 tqfp, e-pad 7mm x 7mm x 1mm package body y package top view
ics8430s10byi-03 revision a february 22 , 2011 2 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors block diagram nlvds_sel 2 2 2 pullup/pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown pulldown
ics8430s10byi-03 revision a february 22 , 2011 3 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors table 1. pin descriptions number name type description 1, 13, 23 v dd power core supply pins. 2 noe_d input pulldown active low output enable for bank d out puts. when logic high, the outputs are high impedance (hi-z). when logic low, the outputs are enabled. lvcmos/lvttl interface levels. 3, 12, 30, 31, 39, 42, 46 gnd power power supply ground. 4 npll_sel input pulldown pll bypass. when low, pll is enabled. when high, pll is bypassed. lvcmos/lvttl interface levels. 5, 6 xtal_in, xtal_out input parallel resonant crystal interface. xtal_out is the output, xtal_in is the input. 7 nxtal_sel input pulldown selects xtal input when low. selects differential clock (pclk, npclk) input when high. lvcmos/lvttl interface levels. 8 pclk input pulldown non-inverting differential clock input. 9 npclk input pullup/ pulldown inverting differential clock input. internal resistor bias to v dd /2. 10 noe_c input pulldown active low output enable for bank c outp ut. when logic high, the output is high impedance (hi-z). when logic low, qc output is enabled. lvcmos/lvttl interface levels. 11 noe_b input pulldown active low output enable for bank b out puts. when logic high, the outputs are high impedance (hi-z). when logic low, the outputs are enabled. lvcmos/lvttl interface levels. 14 noe_a input pulldown active low output enable for b ank a outputs. lvcmos/lvttl interface levels. 15, 16 spi_sel1, spi_sel0 input pulldown selects the spi pll clock reference frequency. see table 3d. 17, 18 pci_sel1, pci_sel0 input pulldown selects the pci, pci-x reference clock output frequency. see table 3c. lvcmos/lvttl interface levels. 19, 20 ddr_sel1, ddr_sel0 input pulldown selects the ddr reference clock output frequency. see table 3b. lvcmos/lvttl interface levels. 21, 22 nqa, qa output differential ou tput pair. selectable between l vpecl and lvds interface levels. 24 v dda power analog supply pin. 25, 28 v ddo_b power bank b output supply pins. 3.3 v or 2.5v supply. 26, 27 qb1, qb0 output single-ended bank b ou tputs. lvcmos/lvttl interface levels. 29 noe_ref input pulldown active low output enabled. when logic high, the qref[2:0] outputs are high impedance (hi-z). when logic low, t he qref[2:0] outputs are enabled. lvcmos/ lvttl interface levels. 32 core_sel input pulldown selects the processor core clock output frequency. the output frequency is 50mhz when low, and 33.333mhz when high. see table 3a. lvcmos/lvttl interface levels. 33, 34 qd1, qd0 output single-end bank d outputs. lv cmos/lvttl interface levels. 35 qc output single-end bank c output. lvcm os/lvttl interface levels. 36 v ddo_cd power bank c and bank d output supp ly pin. 3.3 v or 2.5v supply. pin descriptions continue on the next page.
ics8430s10byi-03 revision a february 22 , 2011 4 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics note: v ddo_x denotes v ddo_b , v ddo_cd , v ddo_e and v ddo_ref. 37 v ddo_e power bank e output supply pin. 3.3 v or 2.5v supply. 38 qe output single-end bank e output. lvcm os/lvttl interface levels. 40 nlvds_sel input pulldown selects between lvds and lvpecl interfac e levels on differential output pair qa and nqa. when low, lvds levels are selected. when high, lvpecl levels are selected. see table 3e. 41, 48 v ddo_ref power bank qref output supply pins. 3.3 v or 2.5v supply. 43, 44, 45 qref2, qref1, qref0 output single-ended reference clock outputs. lvcmos/lvttl interface levels. 47 noe_e input pulldown active low output enable for bank e output. when logic high, the output is high impedance (hi-z). when logic low, the output is enabled. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 2pf c pd power dissipation capacitance (per output) v dd, v ddo_x = 3.465v 10 pf v dd = 3.465v, v ddo_x = 2.625v 10 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance qb[0:1], qc, qd[0:1], qe qref[0:2] v ddo_x = 3.465v 23 ? qb[0:1], qc, qd[0:1], qe qref[0:2] v ddo_x = 2.625v 26 ?
ics8430s10byi-03 revision a february 22 , 2011 5 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors function tables table 3a. control input function table table 3b. control input function table table 3c. control input function table table 3d. control input function table table 3e. control input function table input output frequency core_sel qb[0:1] 0 50mhz (default) 1 33.333mhz inputs output frequency ddr_sel1 ddr_sel0 qa, nqa 0 0 133.333mhz (default) 0 1 100.000mhz 1 0 83.333mhz 1 1 125.000mhz inputs output frequency pci_sel1 pci_sel0 qc 0 0 133.333mhz (default) 0 1 100.000mhz 1 0 66.6667mhz 1 1 33.333mhz inputs output frequency spi_sel1 spi_sel0 qd[0:1] 0 0 100.000mhz (default) 0 1 125.000mhz 1 0 80.000mhz input output levels nlvds_sel qa, nqa 0 lvds (default) 1 lvpecl
ics8430s10byi-03 revision a february 22 , 2011 6 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvcmos power supply dc characteristics, v dd = v ddo_x = 3.3v 5%, t a = -40c to 85c note: v ddo_x denotes v ddo_b , v ddo_cd and v ddo_ref. table 4b. lvcmos power supply dc characteristics, v dd = 3.3v 5%, v ddo_x = 2.5v 5%, t a = -40c to 85c note: v ddo_x denotes v ddo_b , v ddo_cd and v ddo_ref. item rating supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs, v o (lvcmos) -0.5v to v dd + 0.5v outputs, i o (lvds) continuous current surge current 10ma 15ma outputs, i o (lvpecl) continuous current surge current 50ma 100ma package thermal impedance, ja 33.1c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.20 3.3 v dd v v ddo_x output supply voltage 3.135 3.3 3.465 v i dd power supply current 150 ma i dda analog supply current 20 ma i ddo_x output supply current no load, nlvds_sel = 0 39 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.20 3.3 v dd v v ddo_x output supply voltage 2.375 2.5 2.625 v i dd power supply current 150 ma i dda analog supply current 20 ma i ddo_x output supply current no load, nlvds_sel = 0 27 ma
ics8430s10byi-03 revision a february 22 , 2011 7 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors table 4c. lvpecl power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4d. lvds power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4e. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, v ddo_x = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note: v ddo_x denotes v ddo_b , v ddo_cd, v ddo_e and v ddo_ref. symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.20 3.3 v dd v i gnd power supply current nlvds_sel = 1 186 ma i dda analog supply current 20 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.20 3.3 v dd v i dd power supply current nlvds_sel = 0 150 ma i dda analog supply current 20 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current ddr_sel[0:1], npll_sel, nlvds_sel, pci_sel[0:1], noe_ref, spi_sel[0:1], noe_[a:e], nxtal_sel, core_sel v dd = v in = 3.465v 150 a i il input low current ddr_sel[0:1], npll_sel, nlvds_sel, pci_sel[0:1], noe_ref, spi_sel[0:1], noe_[a:e], nxtal_sel, core_sel v dd = 3.465v, v in = 0v -10 a v oh output high voltage v ddo_x = 3.465v, i oh = -12ma 2.6 v v ddo_x = 2.625v, i oh = -12ma 1.8 v v ol output low voltage v ddo_x = 3.465v, i ol = 12ma 0.65 v v ddo_x = 2.625v, i ol = 12ma 0.55 v
ics8430s10byi-03 revision a february 22 , 2011 8 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors table 4f. lvpecl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: common mode input voltage is defined as v ih . note 2: outputs terminated with 50 ? to v dd ? 2v. table 4g. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v dd = v in = 3.465v 150 a i il input low current pclk v dd = 3.465v, v in = 0v -10 a npclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 0.3 1.0 v v cmr common mode input volt age; note 1 gnd + 1.5 v dd v v oh output high voltage; note 2 v dd ? 1.4 v dd ? 0.9 v v ol output low voltage; note 2 v dd ? 2.0 v dd ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 300 600 mv ? v od v od magnitude change 50 mv v os offset voltage 1.04 1.14 1.24 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics8430s10byi-03 revision a february 22 , 2011 9 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors ac electrical characteristics table 6. ac characteristics, v dd = 3.3v 5%, v ddo_x = 3.3v 5% or 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f out output frequency qa, nqa ddr_sel[1:0] = 00 133.333 mhz qa, nqa ddr_sel[1:0] = 01 100 mhz qa, nqa ddr_sel[1:0] = 10 83.333 mhz qa, nqa ddr_sel[1:0] = 11 125 mhz qbx core_sel = 0 50 mhz qbx core_sel = 1 33.333 mhz qc pci_sel[1:0] = 00 133.333 mhz qc pci_sel[1:0] = 01 100 mhz qc pci_sel[1:0] = 10 66.667 mhz qc pci_sel[1:0] = 11 33.333 mhz qdx spi_sel[1:0] = 00 100 mhz qdx spi_sel[1:0] = 01 125 mhz qdx spi_sel[1:0] = 10 80 mhz qe 125 mhz qrefx 25 mhz t sk(b) bank skew; note 1, 2 qrefx using pclk, npclk 25 ps t sk(pp) part-to-part skew; note 2, 3 qrefx using pclk, npclk 350 ps tjit(?) rms phase jitter, (random); note 5 qrefx 25mhz (10khz to 5mhz) 0.637 ps qe 125mhz (1.875mhz to 20mhz) 0.557 ps tjit(per) period jitter (pk-pk); note 4, 11 qa, nqa 133.33mhz; note 6 115 ps 100mhz; note 7 115 ps 133.33mhz; note 8 115 ps 100mhz; note 9 115 ps 83.33mhz; note 10 115 ps qbx 50mhz; note 6 95 ps 50mhz; note 7 95 ps 50mhz; note 8 95 ps 50mhz; note 9 95 ps 50mhz; note 10 95 ps qc 133.33mhz; note 6 90 ps 133.33mhz; note 9 90 ps qdx 100mhz; note 7 95 ps 125mhz; note 8 95 ps 125mhz; note 10 95 ps qe 125mhz; note 6 90 ps 125mhz; note 8 90 ps 125mhz; note 9 90 ps 125mhz; note 10 90 ps continued on next page.
ics8430s10byi-03 revision a february 22 , 2011 10 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at maximum f out, unless noted otherwise. note: all parameters are characterized using crystal input, unless noted otherwise. note: v ddo_x denotes v ddo_b , v ddo_cd, v ddo_e and v ddo_ref. note 1: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs on different devices operati ng at the same supply voltage, same temperature and with eq ual load conditions. using the same type of inputs on each device, the outputs are measured at v ddo_ref /2. note 4: this parameter is measured at the crosspoint for differential and v ddo_x /2 single-ended signals. note 5: refer to the phase noise plot. note 6: ddr_sel[1:0] = 00: qa, nqa = 133.33mhz, qbx = 50mhz, qc = 133.33mhz, qdx = off, qe = 125mhz and qrefx = 25mhz. note 7: ddr_sel[1:0] = 01: qa, nqa = 100mhz, qbx = 50mhz, qc = off, qdx = 100mhz, qe = off and qrefx = 25mhz. note 8: ddr_sel[1:0] = 00: qa, nqa = 133.33mhz, qbx = 50mhz , qc = off, qdx = 125mhz, qe = 125mhz and qrefx = 25mhz. note 9: ddr_sel[1:0] = 01: qa, nqa = 100mhz, qbx = 50mhz, qc = 133.33mhz, qdx = off, qe = 125mhz and qrefx = 25mhz. note 10: ddr_sel[1:0] = 10: qa, nqa = 83.33mhz, qbx = 50mhz , qc = off, qdx = 125mhz, qe = 125mhz and qrefx = 25mhz. note 11: this parameter is measured at 10k cycles. tjit(hper) rms half-period jitter; note 2, 4 qa, nqa 133.33mhz; note 6 30 ps 100mhz; note 7 30 ps 133.33mhz; note 8 30 ps 100mhz; note 9 30 ps 83.33mhz; note 10 30 ps t r / t f output rise/fall time qa, nqa 10% to 90% 150 350 ps qbx, qc, qdx, qe, qrefx 200 900 ps odc output duty cycle qa, nqa 48 52 % qbx, qc, qe, qrefx 48 52 % qdx 48 52 % t lock lock time 55 ms symbol parameter test conditions minimum typical maximum units
ics8430s10byi-03 revision a february 22 , 2011 11 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors typical phase noise at 125mhz (qe output) noise power dbc hz offset frequency (hz)
ics8430s10byi-03 revision a february 22 , 2011 12 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors typical phase noise at 25mhz (qref output) noise power dbc hz offset frequency (hz)
ics8430s10byi-03 revision a february 22 , 2011 13 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit 3.3v core/3.3v lvpecl output load ac test circuit differential input level 3.3v core/2.5v lvcmos output load ac test circuit 3.3v core/3.3v lvds output load ac test circuit lvcmos part-to-part skew scope qx gnd -1.65v5% 1.65v5% v dd, v dda 1.65v5% v ddo_x scope qx nqx lvpecl gnd -1.3v0.165v v dda 2v 2v v dd npclk pclk v dd gnd v cmr cross points v pp - scope qx gnd -1.25v5% v ddo_x 2.05v5% 1.25v5% v dd v dda 2.05v5% scope qx nqx 3.3v5% power supply +? float gnd v dda v dd t sk(pp) v ddo_x 2 v ddo_x 2 part 1 part 2 qrefx qrefy
ics8430s10byi-03 revision a february 22 , 2011 14 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors parameter measurement in formation, continued period jitter, peak-to-peak differential output duty cycle/pulse width/period rms phase jitter half period jitter lvcmos output duty cycle/pulse width/period lvcmos bank skew v oh v ref v ol mean period (first edge after trigger) 10,000 cycles reference point (trigger edge) histogram t jit (pk-pk) t pw t period t pw t period odc = x 100% qa nqa offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power ? ? ? ? ?? half period n t half period n + 1 1 f o t jit(hper) = t half period n ? 1 2*f o qa nqa t period t pw t period odc = v ddo_x 2 x 100% t pw qbx, qc, qdx, qe, qrefx t sk(b) v ddo_x 2 v ddo_x 2 qref{0:2] qref{0:2]
ics8430s10byi-03 revision a february 22 , 2011 15 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors parameter measurement in formation, continued lvds output rise/fall time lvcmos output rise/fall time offset voltage setup lvpecl output rise/fall time lock time differential output voltage setup 10% 90% 90% 10% t r t f v od qa nqa 10% 90% 90% 10% t r t f qbx, qc, qdx, qe, qrefx out out lvds dc input v os / ? v os v dd 10% 90% 90% 10% t r t f v swing qa nqa 100 out out lvds dc input v od / ? v od v dd
ics8430s10byi-03 revision a february 22 , 2011 16 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors applications information recommendations for unused input and output pins inputs: pclk/npclk inputs for applications not requiring the us e of the differential input, both pclk and npclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs the unused lvpecl output pair c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs the unused lvds output pair can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ics8430s10byi-03 revision a february 22 , 2011 17 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors 3.3v lvpecl differentia l clock input interface the pclk /npclk accepts lvpecl, lvds, cml, sstl and other differential signals. the differential signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 2c. pclk/npclk input driven by a 3.3v lvds driver figure 2e. pclk/npclk inpu t driven by a cml driver figure 2b. pclk/npclk input driven by a 3.3v lvpecl driver figure 2d. pclk/npclk input driven by a 3.3v sstl driver r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 pclk npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v lvpecl input c1 c2 pclk npclk vbb 3.3v lvpecl input r1 1k r2 1k 3.3v zo = 50 ? zo = 50 ? c1 c2 r5 100 ? lvds c3 0.1f pclk npclk lvpecl input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 ? r2 50 ? r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl lvpecl input pclk npclk lvpecl input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 ? r2 120 ? r3 120 ? r4 120 ?
ics8430s10byi-03 revision a february 22 , 2011 18 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedanc e of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device wil l be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpecl driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ics8430s10byi-03 revision a february 22 , 2011 19 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential output pair is lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl outp ut termination figure 4b. 3.3v lvpecl output termination lvds driver termination a general lvds interface is shown in figure 5. standard termination for lvds type output stru cture requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 5 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and confirm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. figure 5. typical lvds driver termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _ 100 ? ? + 100 ? differential transmission line lvds driver lvds receiver
ics8430s10byi-03 revision a february 22 , 2011 20 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ics8430s10byi-03 revision a february 22 , 2011 21 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors application schematic figure 7 shows an example of ics8430s10i-03 application schematic. in this example, the device is operated at v dd = v dda = v ddo_b = v ddo_cd = v ddo_e = v ddo_ref = 3.3v. an 18pf parallel resonant 25mhz crystal is used. the load capacitance c1 = 18pf and c2 = 18pf are recommended for frequency accuracy. depending on the parasitics of the pr inted circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with ot her load capacitance s pecifications can be used. this will require adjusting c1 and c2. for this device, the crystal load capacitors are r equired for proper operation. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. th e ics8430s10i-03 provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pi n filter should be placed on the device side of the pcb and the ot her components can be placed on the opposite side. figure 7. ics8430s10i-03 schematic example power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed fo r wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. vddo c8 0.1uf zo = 50 ohm r11 82.5 npll_sel zo = 50 qe vdd c17 0.1uf c12 0.1uf c3 0.01u r12 100 xta l _ i n x1 25mhz 3.3v zo = 50 r4 125 zo = 50 noe_e noe_ref xta l _ o u t set logic input to '0' c2 18pf c16 0.1uf qa0 (u1:23) vdd pci_sel1 r10 82.5 lvpecl termi nat ion spi_sel1 c15 10uf 3.3v (u1:37) vdd vdd logic control input examples noe_b 3.3v r5 133 lvpecl driv er clk qa0 (u1:48) vdd core_sel vddo_ref receiv er zo = 50 c14 0.1uf vddo ru1 1k ru2 not install (u1:25) ddr_sel0 zo = 50 ohm c13 0.1uf blm18bb221sn1 ferrite bead 1 2 pci_sel0 r3 125 (u1:13) nqa0 c4 10u rd1 not install r1 27 vddo c6 10uf nclk vddo_cd = vddo_e= vddo_ref = 3.3v vdd= vddo_b = 3.3v r8 84 lvds termi nat ion spi_sel0 r6 133 nqa0 c5 0.1uf vdd c10 10uf (u1:36) c11 0.1uf c1 18pf blm18bb221sn2 ferrite bead 1 2 noe_a zo = 50 ohm to logic input pins c7 0.1uf zo = 50 ohm set logic input to '1' rd2 1k nqa0 s ) (u1:28) c18 0.1uf (u1:41) c19 0.1uf u1 37 38 39 40 41 42 43 44 45 46 47 48 1 2 4 3 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 49 vddo_e qe gnd lvds_sel vddo_ref gnd qref2 qref1 qref0 gnd noe_e vddo_ref vdd noe_d npll_sel gnd xta l _i n xta l _o u t nxtal_sel pclk npclk noe_c noe_b gnd vdda vdd qa nqa ddr_sel0 ddr_sel1 pci_sel0 pci_sel1 spi_sel0 spi_sel1 noe_a vdd vddo_cd qc qd0 qd1 core_sel gnd gnd noe_ref vddo_b qb0 qb1 vddo_b pad noe_c nxtal_sel blm18bb221sn3 ferrite bead 1 2 + - (u1:1) vddo_ref receiv er vdd vddo_ref + - r7 84 lvds_sel qa0 qref0 to logic input pins 3.3v noe_d c9 0.1uf ddr_sel1 r2 27 r9 10 vdda
ics8430s10byi-03 revision a february 22 , 2011 22 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors power considerations (lvcmos/lvds outputs) this section provides information on power dissipati on and junction temperatur e for the ics8430s10i-03. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8430s10i-03 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. core and lvds output power dissipation power (core, lvds) = v dd_max * (i dd + i dda ) = 3.465v * (150ma + 20ma) = 589.05mw lvcmos output power dissipation dynamic power dissipation at 133.33mhz power (133.33mhz) = c pd * frequency * (v ddo ) 2 = 10pf * 133.33mhz * (3.465v) 2 = 16mw per output total power (133.33mhz) = 16mw * 1 = 16mw power(125mhz) = 10pf * 125mhz * (3.465v) 2 = 15mw per output total power (125mhz) = 15mw * 3 = 45mw dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v ddo ) 2 = 10pf * 25mhz * (3.465v) 2 = 3mw per output total power (25mhz) = 3mw * 3 = 9mw power (50mhz) = c pd * frequency * (v ddo ) 2 = 10pf * 50mhz * (3.465v) 2 = 6mw per output total power (50mhz) = 6mw * 2 = 12mw total power dissipation total power = power (core, lvds) + total power (133.33mhz) + total power (125mhz) + total power (25mhz) + total power (50mhz) = 589.05mw + 16mw + 45mw + 9mw + 12mw = 671.05mw
ics8430s10byi-03 revision a february 22 , 2011 23 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 33.1c/w per table 7a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.671w * 33.1c/w = 107.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. table 7a. thermal resistance ja for 48 lead tqfp, epad forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 33.1c/w 27.2c/w 25.7c/w
ics8430s10byi-03 revision a february 22 , 2011 24 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors power considerations (l vcmos/lvpecl outputs) this section provides information on power dissipati on and junction temperatur e for the ics8430s10i-03. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8430s10i-03 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. core and lvpecl outp ut power dissipation power (core) _max = v dd_max * i ee_max = 3.465v * 186ma = 644.49mw power (output) _max = 30mw/loaded output pair lvcmos output power dissipation dynamic power dissipation at 133.33mhz power (133.33mhz) = c pd * frequency * (v ddo ) 2 = 10pf * 133.33mhz * (3.465v) 2 = 16mw per output total power (133.33mhz) = 16mw * 1 = 16mw power(125mhz) = 10pf * 125mhz * (3.465v) 2 = 15mw per output total power (125mhz) = 15mw * 3 = 45mw dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v ddo ) 2 = 10pf * 25mhz * (3.465v) 2 = 3mw per output total power (25mhz) = 3mw * 3 = 9mw power (50mhz) = c pd * frequency * (v ddo ) 2 = 10pf * 50mhz * (3.465v) 2 = 6mw per output total power (50mhz) = 6mw * 2 = 12mw total power dissipation total power = power (core, lvpecl) + total power (133.33mhz) + total power (125mhz) + total power (25mhz) + total power (50mhz) = 644.49mw + 16mw + 45mw + 9mw + 12mw = 726.49mw
ics8430s10byi-03 revision a february 22 , 2011 25 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 33.1c/w per table 7b below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.727w * 33.1c/w = 109.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. table 7b. thermal resistance ja for 48 lead tqfp, epad forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 33.1c/w 27.2c/w 25.7c/w
ics8430s10byi-03 revision a february 22 , 2011 26 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. the lvpecl output driver circuit and termination are shown in figure 8. figure 8. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v dd ? 2v. for logic high, v out = v oh_max = v dd_max ? 0.9v (v dd_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v dd_max ? 1.7v (v dd_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v dd_max ? 2v))/r l ] * (v dd_max ? v oh_max ) = [(2v ? (v dd_max ? v oh_max ))/r l ] * (v dd_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v dd_max ? 2v))/r l ] * (v dd_max ? v ol_max ) = [(2v ? (v dd_max ? v ol_max ))/r l] * (v dd_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v dd v dd - 2v q1 rl 50
ics8430s10byi-03 revision a february 22 , 2011 27 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors reliability information table 8. ja vs. air flow table for a 48 lead tqfp, epad transistor count the transistor count for ics8430s10i-03 is: 9,291 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 33.1c/w 27.2c/w 25.7c/w
ics8430s10byi-03 revision a february 22 , 2011 28 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors package outline and package dimensions package outline - y suffix for 48 lead tqfp, epad table 9. package dimensions 48l tqfp, epad reference document: jedec publication 95, ms-026 jedec variation: abc - hd all dimensions in millimeters symbol minimum nominal maximum n 48 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.50 ref. d3 & e3 3.5 e 0.5 basic l 0.45 0.60 0.75 0 7 ccc 0.08 -hd version exposed pad down -tab, exposed part of connection bar or tie bar 0.20 tab
ics8430s10byi-03 revision a february 22 , 2011 29 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8430S10BYI-03LF ics0s10bi03l ?lead-free? 48 tqfp, epad tray -40 c to 85 c 8430S10BYI-03LFt ics0s10bi03l ?lead-free? 48 tqfp, epad 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics8430s10byi-03 revision a february 22 , 2011 30 ?2011 integrated device technology, inc. ics8430s10i-03 data sheet clock generator for cavium processors revision history sheet rev table page description of change date a t6 9 14 ac characteristics table - deleted cycle-to-cycle jitter specs. parameter measurement information, deleted cycle-to-cycle jitter diagrams. 2/22/11
ics8430s10i-03 data sheet clock generator for cavium processors disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is subj ect to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property righ ts of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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